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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ADV7202 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 simultaneous sampling video rate codec functional block diagram ain1p d/a adc logic i 2 c i/p mux mux sha and clamp sha and clamp sha and clamp a/d a/d ain1m ain2p ain2m ain3p ain3m ain4p ain4m ain5p ain5m ain6p ain6m 8-bit 843khz adc block 12-bit 10-bit d/a 10-bit d/a 10-bit d/a 10-bit dac logic ADV7202 xtal dout [9:0] da c_data [9:0] osd i/p ? dac0 dac1 dac2 dac3 i/p mux mux a/d a/d 12-bit features four 10-bit video dacs (4:2:2, ycrcb, rgb i/p supported) 10-bit video rate digitization at up to 54 mhz agc control ( 6 db) front end 3-channel clamp control up to five cvbs input channels, two component yuv, three s-video, or a combination of the above. simul- taneous digitization of two cvbs input channels aux 8-bit sar adc @ 843 khz sampling giving up to eight general-purpose inputs i 2 c compatible interface with i 2 c filter rgb inputs for picture-on-picture of the rgb dacs optional internal reference power save mode applications picture-on-picture video systems simultaneous video rate processing hybrid set-top box tv systems direct digital synthesis/i-q demodulation image processing general description the ADV7202 is a video rate sampling codec. it has the capability of sampling up to five ntsc/pal/secam video i/p signals. the resolution on the front end digitizer is 12 bits; 2 bits (12 db) are used for gain and offset adjustment. the digitizer has a conversion rate of up to 54 mhz. the ADV7202 can have up to eight auxiliary inputs that can be sampled by an 843 khz sar adc for system monitoring. the back end consists of four 10-bit dacs that run at up to 200 mhz and can be used to output cvbs, s-video, component ycrcb, and rgb. this codec also supports picture-on-picture. the ADV7202 can operate at 3.3 v or 5 v. its monolithic cmos construction ensures greater functionality with lower power dissipation. the ADV7202 is packaged in a small 64-lead lqfp package.
rev. 0 e2e ADV7202especifications 5 v specifications (avdd/dvdd = 5 v 5%, v ref = 1.235 v, r set = 1.2 k , all specifications t min to t max 1 , unless otherwise noted.) parameter min typ max unit test conditions static performance_dac resolution (each dac) 10 bits accuracy (each dac) 10 bits integral nonlinearity + + = = = ? = ? ? = = =
rev. 0 e3e ADV7202 5 v specifications (avdd/dvdd = 5 v 5%, v ref = 1.235 v, r set = 1.2 k , all specifications t min to t max , unless otherwise noted.) parameter min typ max unit test conditions power requirements 1 avdd/dvdd 4.75 5 5.25 v normal power mode i dac 2 22 ma r set = 1.2 k ? = ?
rev. 0 e4e ADV7202especifications parameter min typ max unit condition 2 programmable gain amplifier video adc gain e6 +6 db setup conditions clamp circuitry 3 clamp fine source/sink current 4.0 a clamp coarse source/sink current 0.8 ma clock control 4 dacclk0/dacclk1 27 mhz dual clk dual edge mode dacclk1 5, 6, 7 200 mhz single edge single clock mode dacclk1 27 mhz 4:2:2 mode data setup time, t 12 7 1.5 ns all input modes data hold time, t 13 7 1.5 ns min clock high time, t 10 7 1.5 ns min clock low time, t 11 7 1.5 ns pipeline delay 8 video adc 4 clock cycles reset control reset t tes tt t tt e tt t s s sets re r set t t
rev. 0 e5e ADV7202 3.3 v specifications (avdd/dvdd = 3.3 v 5%, v ref = 1.235 v, r set = 1.2 k , all specifications t min to t max 1 , unless otherwise noted.) parameter min typ max unit test conditions static performance_dac resolution (each dac) 10 bits accuracy (each dac) 10 bits integral nonlinearity + = = = = ? = ? ? = = =
rev. 0 e6e ADV7202especifications 3.3 v specifications (avdd/dvdd = 3.3 v 5%, v ref = 1.235 v, r set = 1.2 k , all specifications t min to t max , unless otherwise noted.) parameter min typ max unit test conditions power requirements 1 avdd/dvdd 3.14 3.3 3.46 v normal power mode i dac 2 18 ma i dsc 3 8m a inputs at supply i adc 4 80 ma sleep mode current 5 350
rev. 0 e7e ADV7202 3.3 v specifications (avdd/dvdd = 3.3 v 5%, v ref = 1.235 v, r set = 1.2 k , all specifications t min to t max 1 , unless otherwise noted.) parameter min typ max unit condition 2 programmable gain amplifier video adc gain e6 +6 db clamp circuitry 3 clamp fine source/sink current 4 =
rev. 0 ADV7202 e8e caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADV7202 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings 1 avdd to avss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v dvdd to dvss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v ambient operating temperature (t a ) . . . . . . . . 0 + reset rset rea at at aa assa at at s s s t t t a a a rea a a se t t t t t t t a ss sa rerrat tr a
rev. 0 ADV7202 e9e pin function descriptions input/ pin no. mnemonic output function 1 sync_in i this signal can be used to synchronize the updating of clamps. polarity is pro- grammable via i 2 c. 2 scl i mpu port serial interface clock input 3 alsb i this signal sets up the lsb of the mpu address. mpu address = 2ch, alsb = 0, mpu address = 2eh, alsb = 1. when this pin is tied high, the i 2 c filter is activated, which reduces noise on the i 2 c interface. when this pin is tied low, the input bandwidth on the i 2 c lines is increased. 4 xtal0 i input terminal for crystal oscillator or connection for external oscillator with cmos-compatible square wave clock signal. 5 xtal1 o second terminal for crystal oscillator. not connected if external clock source is used. 6 avdd_adc p adc supply voltage (5 v or 3.3 v) 7 avss_adc g ground for adc supply 8e19 ain1eain6 i analog signal inputs. can be configured differentially or single-ended. 20 dvss g ground for digital core supply 21 refadc i/o voltage reference input or programmable reference out. 22 cml o common-mode level for adcs. connect a 0.1 f capacitor from cml pin to avss_adc. 23, 24 cap2, cap1 i adc capacitor network. connect a 0.1 f capacitor from each cap pin to avss_adc and a 10 f capacitor across the two cap pins. 25 osden i enable data from osdin0eosdin2 to be switched to the outputs when set to a logic high. 26e35 dout[9:0] o adc data output 36 osdin2 i third input channel for on-screen display 37 osdin1 i second input channel for on-screen display 38 osdin0 i first input channel for on-screen display 39 dac3_out o general-purpose analog output 40 dac2_out o analog output. can be used to output cvbs, r, or u. 41 avss_dac g ground for dac supply 42 avdd_dac p dac supply voltage (5 v or 3.3 v) 43 dac1_out o analog output. can be used to output cvbs, y, g, or luma. 44 dac0_out o analog output. can be used to output cvbs, v, b, or chroma. 45 comp o compensation pin for dacs. connect 0.1 f capacitor from comp pin to avdd_dac. 46 vrefdac i/o dac voltage reference output pin, nominally 1.235 v. can be driven by an external voltage reference. 47 rset i used to control the amplitude of the dac output current, 1200 resistor gives an i max of 4.33 ma. 48 reset r t r ss s s st ss t s s
rev. 0 ADV7202 e10e functional description analog inputs the ADV7202 has the capability of sampling up to five cvbs video input signals, two component yuv, or three s-video inputs. eight auxiliary general-purpose inputs are also available. table i shows the analog signal input options available and pro- grammable by i 2 c. when configured for auxiliary input mode, the cvbs inputs are single-ended with the second differential input internally set to vrefadc. the resolution on the front end digitizer is 12 bits; 2 bits (12 db) are used for gain and offset adjustment. the digitizer has a conversion rate of up to 54 mhz. the eight auxiliary inputs can be used for system monitoring, etc. and are sampled by an 843 khz * sar adc. the analog input signal range will be dependent on the value of vrefadc and the sha gain see (table ii). three on-screen display inputs osdin[2:0] mux to the dac outputs to enable support for picture-on-picture applications. table i. analog input signal data register sha setting description used sync_out 0000 cvbs in on ain1 0 figure 1 0001 cvbs in on ain2 0 figure 1 0010 cvbs in on ain3 1 figure 1 0011 reserved 1 0100 cvbs in on ain5 0 figure 1 0101 cvbs in on ain6 2 figure 1 0110 y/c, y on ain1, c on ain4 0, 1 figure 2 0111 y/c, y on ain2, c on ain3 0, 1 figure 2 1000 yuv, y on ain2, u on ain3, 0, 1, 2 figure 3 v on ain6 1001 cvbs on ain1 and 8 aux. 0 figure 1 i/ps ain3eain6 * . 1010 cvbs on ain2 and 8 aux. 0 figure 1 i/ps ain3eain6 * . * aux inputs are single-ended. all other inputs are differential. * fclk/32, 843 khz for nominal 27 mhz table ii. analog input signal range sha input range (v) i/p mode v refout (v) gain min max differential 2.2 1 e2.2 +2.2 differential 2.2 2 e1.1 +1.1 differential 1.1 1 e1.1 +1.1 differential 1.1 2 e0.55 +0.55 single-ended 2.2 1 0 4.4 single-ended 2.2 2 1.1 3.3 single-ended 1.1 1 0 2.2 single-ended 1.1 2 0.55 1.65 digital inputs the dac digital inputs on the ADV7202 [9:0] are ttl compatible. data may be latched into the device in three different modes, programmable via i 2 c. dac mode 1, single clock, single edge (see figure 10) uses only the rising edge of dacclk1 to latch data into the device. dacclk0 is a data line that goes high to indicate that the data is for dac0. subsequent data-words go to the next dac in sequence. dac mode 2, dual edge, dual clock (see figure 11) clocks data in on both edges of dacclk0 and dacclk1. using this option, data can be latched into the device at four times the clock speed. all four dacs are used in this mode. dac mode 3, 4:2:2 mode (see figure 12). using this option, 4:2:2 video data is latched in using dacclk1, while dacclk0 is used as a data line that is brought to a high state when cr data is input; hence y will appear on dac1, cr on dac2, and cb on dac0. analog outputs analog outputs [dac0edac3] consist of four 10-bit dacs that run at up to 54 mhz or up to 200 mhz if only dac0 is used. these outputs can be used to output cvbs, s-video, compo- nent ycrcb, and rgb. digital outputs video data will be clocked out on dout[9:0] on the rising edge of xtal0 (see figure 13). auxiliary data can be read out via i 2 c compatible mpu port. i 2 c control i 2 c operation allows both reading and writing of system registers. its operation is explained in detail in the mpu port descrip- ti on section.
rev. 0 ADV7202 e11e video clamping and agc control when analog signal clamping is required, the input signal should be ac-coupled to the input via a capacitor, the clamping control is via the mpu port. the agc is implemented digitally. for cor- rect operation, the user must program the clamp value to which the signal has been clamped into the ADV7202 i 2 c register. this allows the user to specify which signal level is unaffected by the agc. the digital output signal will be a function of the adc output, the agc gain, and the clamp level and can be repre- sented as follows: d agc gain adc data clamp level clamp level out = [] + _? (1) d out will be a 10-bit number (0e1023), the agc gain de faults to 2 and can have a value between 0 to 7.99. the clamp l evel is a 10-bit number (0e1023) equal to the 7-bit i 2 c value 16 (clamp level cr06-cr00); the adc value can be regarded as a 10-bit number (0e1023) for the equation. it should be noted that the adc resolution is 12 bits. the above equation is used to give a basic perspective and is mathematically correct. when the clamps are operational, equation 1 shows how the ADV7202 ensures that the level to which the user is clamping is unaffected by the agc loop. when no clamps are operational, the operation should be regarded as a straightforward gain-and- level shift. equation 1 maps the adc input voltage range to its output. agc gain the agc gain can be set to a value from 0 to 7.99. the agc gain r egister holds a 12-bit number that corresponds to the required gain. the first three msbs hold the gain integer value while the remaining nine bits hold the gain fractional value. the new agc multiplier is latched when the msb register is written to. example: the user requires a gain of 3.65. the first three bits give the integer value 3, hence these will be set to ?011.? the remaining nine bits will have to be set to give the fractional value 0.65, 512 0.65 = 333 = ?101001101.? from equation 2 it can be seen that the clamp level is subtracted from the signal before agc is applied and then added on again after- wards; hence, if the agc gain is set to a value of one, the result would be as follows: ( agc gain = 1) d adc data clamp level clamp level adc data out =+ = _? _ (2) functional description clamp and agc control the ADV7202 has a front end 3-channel clamp control. to perform an accurate agc gain operation, it is necessary to know to what level the user is clamping the black level; this value is program- mable in clamp register 0 cr00ecr06. each channel has a fine and coarse clamp; the clamp direction and its duration are pro- grammable. synchronization of the clamps and agc to the input signal is possible using the sync_in control pin and setting mode r egister cr14 to logic level 1. using this method, it is possible to ensure that agc and clamping are only applied outside the active video area. control signals the function and operation of the sync_in signal is described in the clamp and agc control section. the sync_out will go high while cr data from a ycrcb data stream or c data from a y/c data stream has been output on dout[9:0] (see figures 1 to 3). i 2 c filter a selectable internal i 2 c filter allows significant noise reduction on the i 2 c interface. in setting alsb high, the input bandwidth on the i 2 c lines is reduced and pulses of less than 50 ns are not passed to the i 2 c controller. setting alsb low allows greater input bandwidth on the i 2 c lines. xtal0 cvbs dout [9:0] sync_out cvbs cvbs cvbs cvbs cvbs cvbs figure 1. sync_out output timing, cvbs input xtal0 dout [9:0] sync_out ycyc y cy figure 2. sync_out output timing, y/c (s-video) input
rev. 0 ADV7202 e12e xtal0 dout [9:0] sync_out cr y cb y cr y cb figure 3. sync_out output timing, ycrcb input mpu port description the ADV7202 supports a 2-wire serial (i 2 c-compatible) mi croprocessor bus driving multiple peripherals. two inputs, serial data (sda) and serial clock (scl), carry information between any device connected to the bus. each slave device is recognized by a unique address. the ADV7202 has four pos- sible slave addresses for both read and write operations. these are unique addresses for each device and are illustrated in fig ure 4. the lsb sets either a read or write operation. logic level ??corresponds to a read operation, while logic level ??corresponds to a write operation. a1 is set by setting the alsb pin of the ADV7202 to logic level ??or logic level ?.?when alsb is set to ?,?there is greater input bandwidth on the i 2 c lines, which allows high speed data transfers on this bus. when alsb is set to ?,?there is reduced input band- width on the i 2 c lines, which means that pulses of less than 50 ns will not pass into the i 2 c internal controller. this mode is recomm ended for noisy systems. 001011a1x 0 disabled 1e nabled read/write control set up by alsb address control figure 4. slave address to control the various devices on the bus, the following proto- col must be followed. first, the master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on sda while scl remains high. this indicates that an ad dress/ data stream will follow. all peripherals respond to the start condition and shift the next eight bits (7-bit address + r/ w bit). the bits are transferred from msb down to lsb. the periph- eral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. this is known as an acknowledge bit. all other devices withdraw from the bus at this point and maintain an idle condition. the idle condition is where the device monitors the sda and scl lines waiting for the start condition and the correct transmitted address. the r/ w bit determines the direction of the data. a logic ??on the lsb of the first byte means that the master will write information to the peripheral. a logic ??on the lsb of the first byte means that the master will read information from the peripheral. the ADV7202a acts as a standard slave device on the bus. the data on the sda pin is eight bits long, supporting the 7-bit addresses plus the r/ w bit. it interprets the first byte as the device address and the second byte as the starting subaddress. the subaddresses auto-increment, allowing data to be written to or read from the starting subaddress. a data transfer is always terminated by a stop condition. the user can access any unique subaddress register one-by-one, without updating all the registers. stop and start conditions can be detected at any stage during the data transfer. if these conditions are asserted out of se quence with normal read and write operations, they cause an immediate jump to the idle condition. during a given scl high period, the user should only issue one start condition, one stop condition, or a single stop condition followed by a single start condition. if an invalid subaddress is issued by the user, the ADV7202 will not issue an acknowledge and will return to the idle condition. if in auto-increment mode, the user exceeds the highest subaddress, the following action will be taken: 1. in read mode, the highest subaddress register contents will continue to be output until the master device issues a no-acknowledge. this indicates the end of a read. a no-acknowledge condition is where the sda line is not pulled low on the ninth pulse. 2. in write mode, the data for the invalid byte will not be loaded into any subaddress register, a no-acknowledge will be issued by the ADV7202, and the part will return to the idle condition. figure 5 illustrates an example of data transfer for a read se quence and the start and stop conditions. 1? 8 9 1? 8 9 1? 8 9 p s start addr r/ w a saress a ata a st sata s t
rev. 0 ADV7202 e13e ss lave addr a(s) sub addr a(s) data a(s) data a (s) p ss lave addr a(s) sub addr a(s) data a(m) data a (m) p s slave addr a(s) lsb = 0 lsb = 1 write sequence read sequence s = start bit p = stop bit a(s) = acknowledge by slave a(m) = acknowledge by master a (s) = no-acknowledge by slave a (m) = no-acknowledge by master figure 6. write and read sequence t 3 t 2 t 6 t 1 t 7 t 3 t 4 t 8 sda scl t 5 figure 7. i 2 c mpu port timing diagram t 12 t 11 dacclk1 t 13 data data t 10 data [9:0] dacclk0 t 10 e clock high time t 11 e clock low time t 12 e data setup time t 13 e data hold time figure 8. input data format timing diagram single clock t 12 t 12 t 13 t 13 t 10 t 12 t 13 t 11 t 12 t 13 data data data data da cclk0 da cclk1 da c_data[9:0] data t 10 e clock high time t 11 e clock low time t 12 e data setup time t 13 e data hold time figure 9. input data format timing diagram dual clock
rev. 0 ADV7202 e14e digital data input timing diagrams da c_data [9:0] da cclk0 da cclk1 a1 a2 a3 dac0 dac1 dac2 dac0 dac1 dac2 dac0 a0 at a3, new dac0 data is clocked in and a0, a1, and a2 are sent to the dacs. data appears at t h e output dacs two clock cycles after being sent to the dacs. figure 10. dac mode 1, single clock, single edge input data format timing diagram* * the figure shows three dac usages. dacclk0 is a data line that indicates the data is for dac0. dac1 dac2 dac3 dac0 da c_data [9:0] da cclk0 da cclk1 a1 a2 a3 a4 a1 dac1 data clocked in. a2 dac2 data clocked in. a4 new dac0 data is clocked in and a0, a1, a2, and a3 are sent to the dacs. data appears at the output two clock cycles after being sent to the dacs. a3 dac3 data clocked in. dac1 dac2 dac3 dac0 figure 11. dac mode 2, dual clock, dual edge input data format timing diagram dac1 dac2 da c_data [9:0] da cclk0 da cclk1 a1 a2 a3 a4 at a4, previous a0, a2, and a3 data is sent to th e dacs. at a2, a1 data is sent to the da cs. data appears at the output dacs 2 clock cycles after being sent to th e dacs. dac0 dac1 dac2 dac1 dac0 a0 figure 12. dac mode 3, 4:2:2 input data format timing diagram t 14 t 15 t 15 data data xtal0 output adc o/p dout[9:0] sync_out, sync_in t 14 ?access time t 15 ?hold time figure 13. digital o/p timing
rev. 0 ADV7202 e15e xtal0 data dout [9:0] data data data data data data data figure 14. standard mode digital data o/p format register programming the following section describes the functionality of each register. all registers can be read from as well as written to. subaddress register (sr7?r0) the communications register is an 8-bit write-only register. after the part has been accessed over the bus, and a read/write operation is selected, the subaddress is set up. the subaddress register determines to/from which register the operation takes place. figure 15 shows the various operations under the control of the subaddress register. ??should always be written to sr7. register select (sr6?r0) these bits are set up to point to the required starting address. sr4 sr3 sr2 sr1 sr0 sr6 sr5 address sr6 sr5 sr4 sr3 sr2 sr1 sr0 00h 0 00 0000 mode regi ster 0 01h 0 00 0001 mode regi ster 1 02h 0 00 0010 mode regi ster 2 03h 0 00 0011 mode regi ster 3 04h 0 00 0100 agc regi ster 0 05h 0 00 0101 agc regi ster 1 06h 0 00 0110 clamp regi ster 0 07h 0 00 0111 clamp regi ster 1 08h 0 00 1000 clamp regi ster 2 09h 0 00 1001 clamp regi ster 3 0ah 0 00 1010 tim ing register 0bh 0 00 1011 v ref adjust register 0ch 0 00 1100 r eserved 0dh 0 00 1101 r eserved 0e h0 00 1110 r eserved 0f h0 00 1111 r eserved 10h 0 01 0000 aux regi ster 0 11h 0 01 0001 aux regi ster 1 12h 0 01 0011 aux regi ster 2 13h 0 01 0000 aux regi ster 3 14h 0 01 0100 aux regi ster 4 15h 0 01 0101 aux regi ster 5 16h 0 01 0110 aux regi ster 6 17h 0 01 0111 aux regi ster 7 ADV7202 register sr7 figure 15. subaddress registers register access the mpu can write to or read from all of the registers of the ADV7202 except the subaddress registers, which are write-only. the subaddress register determines which register the next read or write operation accesses. all communications with the part through the bus start with an access to the subaddress register. a read/write operation is then performed from/to the target address which then increments to the next address until a stop command on the bus is performed.
rev. 0 ADV7202 e16e mode register 0 mr0 (mr07emr00) (address (sr4esr0) = 00h) figure 16 shows the various operations under the control of mode register 0. mr0 bit description adc reference voltage (mr00) this control bit is used to select the adc reference voltage. when this bit is set to 0, a reference voltage of 1.1 v is selected. when the bit is set to 1, a reference voltage of 2.2 v is selected. external reference enable (mr01) setting this bit to 1 enables an external voltage reference for the adc. voltage reference power-down (mr02) setting this bit to 1 causes the internal dac voltage refer ence to power down. adc power-down (mr03) setting this bit to 1 causes the video rate adc to power down. power-down (mr04) setting this bit to 1 puts the device into power-down mode. reserved (mr05emr07) zero must be written to these bits. mr01 mr07 mr02 mr04 mr06 mr03 mr00 mr04 0 normal 1power -down power-down mr02 0 normal 1power -down v ref power-down mr00 0 1.1v 1 2.2v adc ref vo ltag e mr03 0 normal 1power -down adc power-down mr01 0 internal 1 external ext ref enable mr05 zero must be written to these bits mr07?r05 figure 16. mode register 0 mode register 1 mr1 (mr17?r10) (address (sr4?r0) = 01h) figure 17 shows the various operations under the control of mode register 1. mr1 bit description dac0 control (mr10) setting this bit to ??enables dac0; otherwise, this dac is powered down. dac1 control (mr11) setting this bit to ??enables dac1; otherwise, this dac is powered down. dac2 control (mr12) setting this bit to ??enables dac2; otherwise, this dac is powered down. dac3 control (mr13) setting this bit to ??enables dac3; otherwise, this dac is powered down. dual edge clock (mr14) setting this bit to ??allows data to be read into the dacs on both edges of the clock; hence, data may be read in at twice the clock frequency. see figure 17. if this bit is set to ?,?the data will only be strobed on the rising edge of the clock. dual clock (mr15) setting this bit to ??allows the use of two clocks to strobe data into the dacs. see figure 17. it is possible to clock data in with only one clock and use the second clock to contain timing information. 4:2:2 mode (mr16) setting this bit to ??enables data to be input in 4:2:2 format. 4:2:2 mode will only work if mr14 and mr15 register bits are set to zero. dac input invert (mr17) setting this bit to ??causes the input data to the dacs to be inverted allowing for an external inverting amplifier. mr17 mr12 mr14 mr16 mr14 0s ingle edge 1dual edge dual edge clock mr15 mr16 0 disable 1e nable 4:2:2 mode mr15 0s ingle clk 1dual clk dual clock mr13 mr11 mr10 mr13 0 normal 1power -down dac 3 control mr17 0 disable 1e nable dac i/p invert mr12 0 normal 1power -down dac 2 control mr10 0 normal 1power -down dac 0 control mr11 0 normal 1power -down dac 1 control figure 17. mode register 1
rev. 0 ADV7202 e17e mode register 2 mr2 (mr20emr27) (address (sr4esr0) = 02h) figure 18 shows the various operations under the control of mode register 2. mr2 bit description analog input configuration (mr20emr23) this control selects the analog input configuration, up to five cvbs input channels, or two component yuv, or three s-v ideo and eight auxiliary inputs. see figure 18 for details. sha0 control (mr24) setting this bit to 0 enables sha0; otherwise, this sha is powered down (sha = sample and hold amplifier). sha1 control (mr25) setting this bit to 0 enables sha1; otherwise, this sha is powered down. sha2 control (mr26) setting this bit to 0 enables sha2; otherwise, this sha is powered down. aux control (mr27) setting this bit to 0 enables the auxiliary adc; otherwise, aux adc is powered down. analog input configuration mr23 mr22 mr21 mr20 0 0 0 0 cvbs in on ain1 0 0 0 1 cvbs in on ain2 00 10 cvbs in on ain3 0 0 1 1 reserved 01 00 cvbs in on ain5 01 01 cvbs in on ain6 01 10 y/c in on ain1, ain4 0 1 1 1 y/c in on ain2, ain3 1 0 0 0 yuv in on ain2, ain3, ain6 1 0 0 1 cvbs in on ain1, 8 aux inputs 10 10 cvbs in on ain2, 8 aux inputs mr21 mr27 mr22 mr24 mr26 mr23 mr20 mr25 mr26 0 normal 1power -down sha2 control mr27 0 normal 1power -down au x control mr25 0 normal 1power -down sha1 control mr24 0 normal 1power -down sha0 control figure 18. mode register 2 mode register 3 mr3 (mr30?r37) (address (sr4?r0) = 03h) figure 19 shows the various operations under the control of mode register 3. mr3 bit description clamp current (mr30) setting this bit to ??enables the halving of all clamp currents. analog input mode (mr31) setting this bit to ??enables differential mode for the analog inputs; otherwise, the inputs are single-ended. see figure 19. sha gain (mr32) setting this bit to ??enables sha gain of 1. if the bit is set to ?, the sha gain is 2. the sha gain will limit the input signal range. see figure 19. voltage clamp (mr33) setting this bit to ??will enable the voltage clamps. output enable (mr34) setting this bit to ??puts the digital outputs into high impedance. sync polarity (mr35) this bit controls the polarity of the sync_in pin. if the bit is set to ?,?a logic low pulse corresponds to h-sync. if the bit is ?, a logic high pulse corresponds to h-sync. this sync in pulse can then be used to control the synchronization of agc/clamping. see ar12. reserved (mr36?r37) zero must be written to both these registers. mr37 mr32 mr34 mr36 mr34 0 normal 1 high z output enable mr35 mr35 0low 1 high sync polarity mr33 mr31 mr30 mr33 0off 1on vo ltag e clamp mr32 01 12 sha gain mr30 0 normal 1 half clamp current mr31 0s ingle-ended 1 differential analog input mr37?r36 zero must be written to these registers figure 19. mode register 3
rev. 0 ADV7202 e18e agc register 0 ar0 (ar00ear07) (address (sr4esr0) = 04h) figure 20 shows the various operations under the control of agc register 0. ar0 bit description agc multiplier (ar00ear07) this register holds the last eight bits of the 12-bit agc multiplier word. agc register 1 ar1 (ar08ear15) (address (sr4esr0) = 05h) figure 20 shows the various operations under the control of agc register 1. ar1 bit description agc multiplier (ar08ear11) these registers hold the first four bits of the 12-bit agc multiplier word. agc sync enable (ar12) setting this bit to 1 forces the agc to wait until the next sync pulse before switching on. reserved (ar13ear15) zero must be written to these registers. ar07 ar02 ar04 ar06 ar05 ar03 ar01 ar00 ar12 0off 1on ag c sync enable ar15?r13 zero must be written to these registers ar11?r00 12-bit agc multiplier ar00, holds the lsb, ar11 the msb agc mult iplier ar15 ar10 ar12 ar14 ar13 ar11 ar09 ar08 figure 20. agc registers 0?
rev. 0 ADV7202 e19e clamp register 0 cr0 (cr00ecr07) (address (sr4esr0) = 06h) figure 21 shows the various operations under the control of clamp register 0. cr0 bit description clamp level/16 (cr00ecr06) to perform an accurate agc gain operation, it is neces sary to know to what level the user is clamping the black level. this black level is then subtracted from the 10-bit adc output be fore gaining. it is then added on again afterwards. it should be noted that this register is seven bit and will hold the value of clamp value/16. reserved (cr07) zero must be written to this bit. clamp register 1 cr1 (cr10ecr17) (address (sr4esr0) = 07h) figure 22 shows the various operations under the control of clamp register 1. cr1 bit description fine clamp on time (cr10ecr12) there are three fine clamp circuits on the chip. this word con trols the number of clock cycles for which the fine clamps are switched on per video line. the clamp is switched on after a sync pulse is received on the sync_in pin, provided the relevant enabling bit is set (see cr16). coarse clamp on time (cr13ecr15) there are three coarse clamp circuits on the chip. this i 2 c word controls the number of clock cycles for which the fine clamps are switched on per video line. the clamp is switched on after a sync pulse is received on the sync_in pin, provided the relevant enabling bit is set (see cr16). synchronize clamps (cr16) setting this bit to 1 forces the clamps to wait until the next sync pulse before switching on. reserved (cr17) zero must be written to this bit. cr07 cr02 cr04 cr06 7-bit [6:0] clamp level, cr00 holds the lsb, cr06 the msb cr06?r00 cr05 cr03 cr01 cr00 clamp level zero must be written to this bit cr07 figure 21. clamp register 0 cr11 cr17 cr12 cr14 cr15 zero must be written to this bit cr17 cr13 cr10 cr16 cr16 0off 1on synchronize clamps cr12 cr11 cr10 00 02 clock cycles 00 14 clock cycles 01 08 clock cycles 01 1 16 clock cycles 10 0 32 clock cycles 10 1 64 clock cycles 11 0 128 clock cycles 11 1 256 clock cycles fine clamp on time cr15 cr14 cr13 00 02 clock cycles 00 14 clock cycles 01 08 clock cycles 01 1 16 clock cycles 10 0 32 clock cycles 10 1 64 clock cycles 11 0 128 clock cycles 11 1 256 clock cycles coarse clamp on time figure 22. clamp register 1
rev. 0 ADV7202 e20e clamp register 2 cr2 (cr20ecr27) (address (sr4esr0) = 08h) figure 23 shows the various operations under the control of clamp register 2. cr2 bit description fine clamp 0 up/down (cr20) this bit controls the direction of fine clamp number 0, valid only if the clamp is enabled. fine clamp 0 on/off (cr21) this bit switches fine clamp number 0 on for the prescribed number of clock cycles (cr10ecr12). fine clamp 1 up/down (cr22) this bit controls the direction of fine clamp number 1, valid only if the clamp is enabled. fine clamp 1 on/off (cr23) this bit switches fine clamp number 1 on for the prescribed number of clock cycles (cr10ecr12). fine clamp 2 up/down (cr24) this bit controls the direction of fine clamp number 2, valid only if the clamp is enabled. fine clamp 2 on/off (cr25) this bit switches fine clamp number 2 on for the prescribed number of clock cycles (cr10ecr12). reserved (cr26ecr27) zero must be written to these registers. cr27 cr22 cr24 cr26 zero must be written to these registers cr27?r26 cr24 0down 1up fine clamp 2 up/down cr25 cr23 cr21 cr20 cr22 0down 1up fine clamp 1 up/down cr20 0down 1up fine clamp 0 up/down cr25 0off 1on fine clamp 2 on/off cr23 0off 1on fine clamp 1 on/off cr21 0off 1on fine clamp 0 on/off figure 23. clamp register 2 clamp register 3 cr3 (cr30?r37) (address (sr4?r0) = 09h) figure 24 shows the various operations under the control of clamp register 3. cr3 bit description coarse clamp 0 up/down (cr30) this bit controls the direction of coarse clamp number 0, valid only if the clamp is enabled. coarse clamp 0 on/off (cr31) this bit switches coarse clamp number 0 on for the prescribed number of clock cycles (cr13?r15). coarse clamp 1 up/down (cr32) this bit controls the direction of coarse clamp number 1, valid only if the clamp is enabled. coarse clamp 1 on/off (cr33) this bit switches coarse clamp number 1 on for the prescribed number of clock cycles (cr13?r15). coarse clamp 2 up/down (cr34) this bit controls the direction of coarse clamp number 2, valid only if the clamp is enabled. coarse clamp 2 on/off (cr35) this bit switches coarse clamp number 2 on for the prescribed number of clock cycles (cr13?r15). reserved (cr36?r37) zero must be written to these registers. cr34 cr37 cr32 zero must be written to these registers cr37?r36 cr35 0off 1on coarse clamp 2 on/off cr34 0down 1up coarse clamp 2 up/down cr33 0off 1on coarse clamp 1 on/off cr32 0down 1up coarse clamp 1 up/down cr30 0down 1up coarse clamp 0 up/down cr31 0off 1on coarse clamp 0 on/off cr36 cr35 cr33 cr31 cr30 figure 24. clamp register 3
rev. 0 ADV7202 e21e timing register tr (tr00etr07) (address (sr4esr0) = 0ah) figure 25 shows the various operations under the control of the timing register. tr bit description crystal oscillator circuit (tr00) if this bit is set to 0, the internal oscillator circuit will be disabled. disabling the oscillator circuit is possible when an external clock module is used, thus saving power. adc bias currents (tr01) if this bit is set to 1, all analog bias currents will be doubled. duty cycle equalizer (tr03) when this bit is set to 1, the clock duty cycle equalizer circuit is active. this will only have an effect on the adc operation. the digital core clock will not be affected. clock delay (tr05etr06) using these two bits, it is possible to insert a delay in the clock signal to the digital core. these bits control the insertion of the delay. reserved (tr02, tr04, tr07) zero must be written to the bits in these registers. tr01 tr02 tr04 tr05 tr06 zero must be written to this bit tr07 tr03 tr00 tr00 0 disable 1e nable crystal oscillator circuit tr06 tr05 00 0n s 01 4n s 10 6n s 11 8n s clock delay tr03 0 inactive 1act ive duty cycle equalizer tr01 0 normal 1 double adc bias currents zero must be written to this bit zero must be written to this bit tr04 tr02 tr07 figure 25. timing register 0 vref adjust register vr (vr00?r07) (address (sr4?r0) = 0bh) figure 26 shows the various operations under the control of the vref adjust register. vr bit description reserved (vr00) this register is reserved and ??must be written to this bit. reserved (vr01?r03) zero must be written to these registers. adc reference voltage adjust (vr04?r06) by setting the value of this 3-bit word, it is possible to trim the adc internal voltage reference vrefadc. reserved (vr07) zero must be written to this register. vr01 vr07 vr02 vr04 vr05 vr06 zero must be written to this bit vr07 vr03 vr00 vr06 vr05 vr04 00 0d efault nominal 00 1 + 14mv 01 0 + 28mv 01 1 + 42mv 10 0 ?4mv 10 1 ?8mv 11 0 ?2mv 11 1 ?6mv adc reference voltage adjust zero must be written to these bits vr03?r01 one must be written to this bit vr00 figure 26. adc vref register
rev. 0 ADV7202 e22e auxiliary monitoring registers au (au00eau07) (address (sr4esr0) = 10h) there are eight auxiliary monitoring registers. these registers are read-only; when the device is configured for auxiliary inputs, a u01 a u07 a u02 a u04 a u05 a u06 8-bit [7:0] value corresponding to au x0 input value a u07?u00 a u03 au00 au x register 0 figure 27. aux register 0 a u09 a u15 a u10 a u12 a u13 a u14 8-bit [7:0] value corresponding to au x1 input value a u15?u08 a u11 au08 au x register 1 figure 28. aux register 1 a u17 a u23 a u18 a u20 a u21 a u22 8-bit [7:0] value corresponding to au x2 input value a u23?u16 a u19 au16 au x register 2 figure 29. aux register 2 a u25 a u31 a u26 a u28 a u29 a u30 8-bit [7:0] value corresponding to au x3 input value a u31?u24 a u27 au24 au x register 3 figure 30. aux register 3 they will display a value corresponding to the converted auxiliary input. auxiliary register 0 will contain the value of the con- verted auxiliary 0 input, auxiliary register 1 the value of the converted auxiliary 1 input, and so on to auxiliary register 7.
rev. 0 ADV7202 e23e a u33 a u39 a u34 a u36 a u37 a u38 8-bit [7:0] value corresponding to au x4 input value a u39eau32 a u35 au32 au x register 4 figure 31. aux register 4 a u41 a u47 a u42 a u44 a u45 a u46 8-bit [7:0] value corresponding to au x5 input value a u47eau40 a u43 au40 au x register 5 figure 32. aux register 5 a u49 a u55 a u50 a u52 a u53 a u54 8-bit [7:0] value corresponding to au x6 input value a u55eau48 a u51 au48 au x register 6 figure 33. aux register 6 a u57 a u63 a u58 a u60 a u61 a u62 8-bit [7:0] value corresponding to au x7 input value a u63eau56 a u59 au56 au x register 7 figure 34. aux register 7
rev. 0 ADV7202 e24e clamp control the clamp control has two modes of operation, if the synchronize clamp control bit cr16 (bit-6 address 07h) is set, then the clamps that are enabled will be switched on for the programmed time when triggered by the sync_in control signal, this control signal is edge detected and its polarity can be set by mr35 (bit 5 address 03h). if the synchronize clamp control bit is set to zero, when enabled each clamp will switch on for the programmed time. the clamp control bits are edge detected and the bits must first be reset to zero before the clamps can be switched on again. dac termination and layout considerations resistor r set is connected between the rset pin and avss and is used to control the amplitude of the dac output current. ir amps max set = ? = ?
rev. 0 ADV7202 e25e 23 40 39 45 24 power supply decoupling for each power supply group av d d dvdd 10 f 0.1 f 0.1 f 10 f dvdd 300 comp vrefdac avdd dvdd dac0 dac1 dac2 dac3 ADV7202 ain1eain6 dout[9:0] da c_data[9:0] 6, 42 54 0.1 f dvdd 4.7k unused inputs should be grounded 300 300 43 44 av d d 46 cap1 cap2 0.1 f 10 f 0.1 f 64 21 47 25 4 48 3 scl sda refadc r set osden avss dvss xtal0 reset as s ss
rev. 0 ADV7202 e26e 64-lead plastic quad flatpack [lqfp] (st-64b) dimensions shown in millimeters top view (pins down) 1 16 17 33 32 48 49 64 0.27 0.22 0.17 0.50 bsc 10.00 bsc 1.60 max seating plane 0.75 0.60 0.45 view a 7 3.5 0 0.20 0.09 1.45 1.40 1.35 0.15 0.05 0.08 max coplanarity view a rotated 90 ccw seating plane 12.00 bsc compliant to jedec standards ms-026bcd outline dimensions
e27e
e28e c02602e0e10/02(0) printed in u.s.a.

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